Customer Success Stories
Read about how GRL has helped industry groups and customers achieve success.
- ThunderboltTM – The GRL Story
- GRL SERDES Characterization Services Support SOC Success
- Quick Signal Integrity Troubleshooting Saves Product Launch Timeline
ThunderboltTM – The GRL Story
In early 2011, Intel® Corporation introduced Thunderbolt™, a revolutionary dual protocol I/O. A result of close technical collaboration between Intel and Apple, Thunderbolt™ dramatically increased transfer performance with bi-directional 10 Gbps speed and offered daisy chaining to multiple devices. Intel sought an independent lab to qualify Thunderbolt™ products to the rigorous demands of the specification.
The GRL Solution:
Leveraging our deep expertise in Thunderbolt’s core technologies – PCI Express and DisplayPort – GRL worked closely with Intel and key early adopters to help develop, roll out, and administer a Thunderbolt™ product certification program.
- Worked closely with the key test equipment vendors supporting Thunderbolt™ – Keysight, Tektronix, and Wilder Technologies – to develop and validate Physical Layer Test Methods of Implementation (MOIs). All approved Thunderbolt™ Physical Layer MOIs bear GRL’s logo.
- Contributed to the development of the Thunderbolt™ specification, as well as the Thunderbolt test program itself including reporting and test checklists.
- Worked with early adopters to pre-certify their products, overcome challenges to certification, and successfully introduce Thunderbolt™ products to market.
In 2012, GRL became the world’ first and only independent lab qualified by Intel® Corporation to perform Thunderbolt product certification testing for AV, Storage, and PCI Express Expansion devices.
GRL’s Comprehensive SERDES Characterization
Services Support SOC Success
A semiconductor vendor sought to introduce a high performance SOC with advanced security, high reliability and low power for demanding industrial, military, and communications applications. The SOC incorporated multiple high speed SERDES blocks and DDR3 memory, but the vendor’s internal team lacked experience and expertise in SERDES characterization and the internal resources to manage and execute such a large, demanding test program. Success of this product was critical for the customer’s overall viability.
The GRL Solution:
GRL planned and executed an end-to-end strategy to characterize the electrical performance of this SOC over Process, Voltage, and Temperature (PVT):
- Facilitated definition of the overall test objectives and program plan, assessing tradeoffs between test coverage and cost vis-à-vis their customers’ expectations and internal reporting needs.
- Developed comprehensive test plans addressing electrical characterization of multiple high speed interfaces over PVT including PCI Express, XAUI, and DDR3. The plans addressed test setup, methodology, and channel de-embedding strategy.
- Provided expert guidance on the characterization test board design addressing layout, pre and post-hardware validation strategy, signal and power integrity, and considerations for signal access and thermal testing.
- Provided guidance on device requirements for testing including required test patterns, scripts, and loopback mode.
- Validated the signal integrity of the characterization test board and extracted s-parameters.
- Helped the customer bring up the test setup in GRL’s lab, tune SERDES parameters, optimize test margins, and debug device test modes, board, and scripts.
- Managed the full PVT characterization test program from beginning to end, addressing baseline testing and testing more than 125 PVT test conditions per interface.
- Worked with the customer’s analog design team and 3rd party IP vendor to quickly and efficiently troubleshoot issues that arose in testing and keep the program schedule on track.
- Prepared comprehensive reports for each interface including detailed analysis of results
GRL’s Signal Integrity Troubleshooting Saves Product Launch
A system OEM set an aggressive timeline to launch a notebook computing platform to market. GRL was performing compliance testing on the USB 3.0 Host interface. The platform passed USB 3.0 Transmitter (Tx) electrical compliance, but failed USB 3.0 Receiver (Rx) compliance.
The GRL Solution:
GRL mounted a comprehensive troubleshooting effort led by Director of Signal Integrity Engineering Miki Takahashi. GRL quickly identified the root cause and recommended changes to the PCB design that resolved the issue and kept the product launch schedule on track.
- Reviewed the PCB layout and established a hypothesis that it was not optimized for high speed signaling.
- Performed a TDR measurement, identifying a large impedance mismatch at the USB connector.
- Provided detailed design recommendations to optimize the routing of the USB connector and placement of the ESD device and worked with the customer’s board design team to implement these recommendations.
- Performed VNA/TDR validation on a bare board assembly of the re-worked PCB design to determine that the impedance mismatch had been resolved, and confirmed that the full platform passed USB 3.0 and 2.0 electrical and functional compliance.