Expertise


Technical Expertise
GRL helps customers implement connectivity technologies by providing compliance, characterization, and signal integrity test and debug services. These test services are centered around GRL's expertise in providing a wide range of electrical, protocol, and system level tests to a various connectivity standards.

GRL goes beyond testing and helps customers if they need additional design, modeling, and simulation support in the areas of signal integrity, SERDES, IBIS, as well as IC packaging, PCB, and FPGA/IC design.

As high speed connectivity technologies become faster and more complex, a combination of test, debug and design is all the more essential to successful technology implementation and product release.
Interview with Ross Stenfort of SandForce about the SandForce Trusted Program and GRL
Meet GRL's Experts
At GRL, we feel it's important to know who's testing your products. Our test experts are recognized veterans in the test & measurement and semiconductor industries and can help you with your test, debug, and design needs.
Mike Engbretson, Chief Technology Engineer
Mike spent the last 20 years at Tektronix developing test solutions to support connectivity technologies such as USB, PCI Express, and SATA. Mike is a recognized high speed test guru and was active in the development of the USB 3.0 electrical Compliance Test Spec and is currently the editor of the DisplayPort 1.2 electrical Compliance Test Spec.
Sandy Chang, Taiwan Technical Director
Sandy spent 14 years at J-Micron and Agilent/HP most recently as System Design Manager. Sandy is an expert in SATA, USB, PCI Express, HDMI, DisplayPort, DDR, and Ethernet compliance, characterization, and debug.
Ben Chia, Senior Signal Integrity Consultant
Ben spent 19 years in Rambus and HAL Computer Systems in the field of high speed bus modeling and signal integrity. Ben is an expert in signal integrity measurement/precision probing, DDR2/3 and 10G backplane technologies, and in using Synopsys HSpice, Ansoft HFSS, Agilent ADS, and AtaiTec X2D signal integrity modeling tools to develop PCB, package, connector, signal integrity channel, and IBIS AMI models.
Jay Hidy, Senior Staff Engineer
Jay spent 17 years at LSI most recently as SERDES Characterization Manager. Jay has deep experience in SERDES architecture, and is an expert in XAUI, SATA, SAS, Fibre Channel, PCI Express, Infiniband, and Serial Rapid IO compliance, characterization, and debug.
Tom Purdy, Senior Consultant
Tom spent 25 years at Agilent/HP where he spent most of his career supporting test equipment as an applications engineer. Tom was Agilent's main digital applications engineer in the Western Region for HDMI, DisplayPort, and MIPI. Tom excelled at training customers on how to use Agilent equipment to test these standards.
Eugene Sushansky, Director of Engineering
Eugene spent over 14 years at PLX, a leading supplier of PCI Express semiconductor products. Eugene's engineering responsibilities included IC system architecture, design, verification, and validation for PCI Express and USB 2.0 related products. Eugene is a recognized PCI Express expert, and has actively participated in the PCI-SIG Serial Enabling Group and PICMG Hot Swap committees.
Miki Takahashi, Director Signal Integrity Engineering
Miki spent 15 years at O2Micro, Advanced Chip Express and NEC most recently as Analog Design Manager. Miki is an expert in SERDES design, SD Interfaces (UHS-1, UHS-2), CF Interfaces (CFast, XQD), and JEDEC (DDR, UFS).
Rajaraman Venkatachalam, Software Architect & GRL India Technical Director
Raja spent over 14 years at Tektronix, Intel and Prodigy Technovations leading the development of automated testing solutions for high speed digital interfaces. Raja has deep experience in post-silicon validation methodologies and developing electrical and protocol compliance testing tools, and is an expert in HDMI, MHL, DisplayPort, UniPro, PCI Express, SD, I2C, SPI, UART, and MMC.