IC Characterization and SERDES Tuning
GRL offers the world’s most robust and comprehensive Independent IC Stress (Characterization) Testing and Tuning Services, focused on R&D bench-level characterization of early silicon across Process, Voltage, and Temperature (PVT). Our customers range from small IC and IP design houses to some of the largest and most capable semiconductor and systems firms in the world. They come to us because this challenging, resource intensive activity requires expensive equipment and deep, specialized expertise that remains in short supply, including analog/SERDES design, test methodology and instrumentation, and test automation.
GRL’s has provided comprehensive characterization services for early silicon ranging from 28 Gb/s SERDES, to sub-gigahertz custom memory interfaces, to specialized analog ICs (AFE, A/D converters, etc).
GRL serves as the industry’s Center of Excellence, and no other independent lab comes close to matching GRL’s capabilities in this area.
GRL provides IC Stress (Characterization) Testing and Tuning Services from our labs in Silicon Valley, Taiwan, Japan, China, and India. Contact GRL today to discuss how we can support your IC characterization and validation needs.
GRL’s IC Characterization Center of Excellence
Depending on the customer’s test objectives and individual budget, GRL will:
- Develop a custom test plan
- Assign technical experts to the project
- Develop custom test methodologies
- Develop custom test automation
- “Audit” IP vendor silicon
- Consult on characterization board design & layout
- Perform SI simulation and measurements on characterization boards
- Procure or develop custom test accessories
- Perform debugging and PHY tuning on first silicon
- Perform higher volume bench characterization over multiple PVT corners
- Provide turnkey characterization test setup in customer’s lab using GRL’s Test Automation Framework
GRL helps semiconductor companies better manage and reduce the increasingly unaffordable cost of testing by providing on-demand access to specialized technical experts utilizing high performance test equipment. Pay for only what you use and avoid having high fixed expenses with high maintenance and equipment obsolescence expenses.
Why IC Stress Testing?
Unlike compliance certification testing where the objective is test to “just pass” in the shortest time possible, semiconductor companies must invest enormous amounts of time to properly characterize and understand the performance of their high-speed interfaces in a variety of non-ideal environments. These environments can include extreme temperatures, supply voltages, fast and slow process corners. Moreover, Signal Integrity issues introduced by board design mistakes, noise or interference from clock or other components, and IC SERDES and packaging problems introduce waveform impairments resulting from excessive jitter and Inter-Symbol Interference (ISI) effects.
Semiconductor companies not only have to deal with their own ICs and reference designs; they must also address interoperability with other ICs and systems which may have poor operating margin and barely meet (or even fail) compliance specifications. IC vendors often find that even if root cause stems more from their customer’s system design, responsibility is placed on the IC vendor to “just make it work”.
Semiconductor companies must therefore operate with a mindset of “test to fail”, and spend many weeks and months to find and resolve issues with their design and maximize performance margins. Without proper tuning of their interface designs, ICs (especially at lower process nodes) will often fail to even meet compliance specs for at least 30% of all process, voltage, temperature variation corners.
Semiconductor companies face further challenges and complexity given the heavy dependency on external IP as part of the interface design. As these interfaces get faster with more complicated power management features, SERDES and PHY transceiver designs have become very specialized, with many semiconductor companies using PHY IP from internal or external sources. Validating someone else’s IP and debugging issues when they arise can add significant delays, especially if the IP has not been fully tested or correctly implemented. Given the high costs of IC mask and short time to market windows, avoiding re-spins due to IP issues is critical.