High-Speed Digital Test Forum 2025 – the Munich face-2-face edition
Date: April 8, 2025
Location: Rohde & Schwarz GmbH & Co. KG, Mühldorfstraße 15, 81671 München
Register for the event here
| Time | Title | Presenter |
|---|---|---|
| 08:00 - 09:00 | Check-in | |
09:00 - 09:30 |
Welcome and Keynote Global digitalization, big data and AI: drivers, trends, opportunities and new design challenges: Digitalization is everywhere and with this the demand for increasing processing power and data rates. This applies for data centers and AI, but also for many other areas like autonomous driving, industry automation, aerospace & defense and wireless communication. We will explore major trends and the evolution of the related technologies and will discuss the impact on high-speed designs and their power distribution networks as well as the increasing challenges in signal integrity and power integrity. |
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09:30 - 10:15 |
Power designs for high-speed SOCs with Multi-Phase Buck Converters: The increasing complexity of high-speed system-on-chips (SoCs) and FPGAs poses significant challenges for power design. As functionality and processing power rise, so do the demands on power management. This necessitates the use of multiple power rails and innovative power supply architectures, such as multiphase buck converters. While these converters offer advantages, they also introduce new design and validation complexities, particularly for high-current power rails. Rohde & Schwarz oscilloscopes, equipped with advanced analysis capabilities, can effectively support the testing and analysis of these intricate power designs, allowing engineers to precisely measure and validate the performance of multiphase buck converters. |
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| 10:15 - 10:45 | Coffee Break | |
10:45 - 11:45 |
USB3.2 Interfaces: Signal Integrity Analysis & Compliance Testing: This class is aimed at engineers who test & debug USB interfaces. In particular, we will discuss the details of USB 3.2 Gen 1 and Gen 2 electrical compliance testing. During the session, you will gain insight into the requirements and test setups for transmitter (Tx) and receiver (Rx) tests, covering topics such as spread spectrum clocking, jitter and eye diagram analysis, pre-shoot/de-emphasis, and more. We will examine potential sources of failure if the compliance check fails and discuss the use of tools to help identify the root causes of compliance failures. |
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11:45 - 12:45 |
Automotive Ethernet: The key to unlocking zonal architecture: As the automotive industry looks to developing the future software defined vehicle (SDV), increased levels of autonomous driving requiring more sensors and increased connectivity brings forth challenges of transporting and processing a huge amount of data in the vehicle. To do this in an efficient way, it is necessary to reduce In-Vehicle Network complexity, power consumption and weight, leading to a change from domain-orientated network architecture to zonal architecture. This session focuses on such trends and significant development in In-Vehicle Networks such as 10Base-T1S and MultiGig speeds and how to test these new networks effectively. |
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| 12:45 - 13:45 | Lunch Break | |
13:45 - 14:30 |
DDR Memory Interfaces: Signal Integrity Analysis & Compliance Testing: The integration of DDR and LPDDR devices in systems often causes challenges for signal and power integrity. We will provide an overview about DDR technologies and key parameters for testing. Learn about effective tools for debugging and characterization as well as automated test solutions for conformance verification. Another challenge for DDR testing is the connectivity via interposers. See on a practical example how to de-embed the effects of the interposer correctly and utilize the power of debugging tools such as Zone Trigger or Read/ Write decoding for eye diagram analysis. |
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14:30 - 15:00 |
MIPI D-PHY: Signal Integrity Analysis & Compliance Testing: The MIPI D-PHY interface was originally developed to enable high-speed data transmission between cameras and displays in mobile phones. Today, it has gained widespread adoption in automotive, consumer and industrial applications. Learn about the MIPI D-PHY interface architecture and key parameters of the physical layer. We will provide an overview of the specified conformance tests, highlight challenges unique to these tests and discuss recommended measurement setups. In case of failures, effective tools such as the Advanced Eye Diagram Analysis and Jitter Decomposition can be used to troubleshoot efficiently. |
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15:00 - 15:30 |
Testing DP 1.4a Sources with oscilloscopes - PHY layer compliance: We are going to explore DisplayPort 1.4a physical layer compliance testing for high-speed digital design. After a technology overview and compliance test requirements, we demonstrate how the RTP oscilloscope can streamline verification. Learn how to debug with signal integrity tools like eye diagram analysis, and pinpoint issues by using jitter and noise decomposition utilities. Practical examples illustrate effective troubleshooting for reliable compliance. |
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| 15:30 - 16:00 | Coffee Break | |
16:00 - 16:45 |
Accurate test fixture characterization and de-embedding for correct measurements with oscilloscopes and VNAs in high-speed digital applications: Modern oscilloscopes and VNAs can mathematically remove, i.e. de-embed the lead-ins to the DUT (e.g. test fixtures, probes, etc.) and measure the correct DUT performance at the defined reference planes. This is done by modelling the lead-in via a Touchstone file. We will discuss the various use cases, the method of impedance corrected de-embedding to generate accurate lead-in models with a VNA and share best practice experience. |
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16:45 - 17:30 |
Characterizing the High-Speed Transmission Channel – Measurement Challenges and Advanced Test Tools: High-speed PCB/interconnect design and validation testing poses significant challenges with increasing data rates. Characterizing transmission channels requires higher frequency testing and multi-port setups to effectively analyze the lane-to-lane crosstalk. This presentation shows various use cases as example. Key concerns for achieving accurate and time-efficient measurements are addressed by using specialized tools such as Time Domain and Enhanced Time Domain Analysis, Multiport S-Parameter SNP Assistant, and R&S®ZNrun Cable Compliance Test Automation. |
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Learn more about the one-day event and register on High-Speed Digital Test Forum 2025 page.