USB4® Certification Process & USB4® v2 Update

Written by GRL Team | Jul 18, 2024 4:33:00 AM

USB4® stands for Universal Serial Bus 4, supports higher data up to 80 Gbps (Gen4 x2), higher display resolution (16K resolution with HDR at 60Hz or two 8K displays at 120Hz), and improved interchangeability with other connectors such as USB 3.2®, DisplayPort, and PCIe. Released in 2019, USB4® has provided external devices with a single-cable docking station solution for laptops, desktops, and other host devices. As such, USB4® has been embraced by major chipset manufacturers.

USB4® v2 was later announced by the USB® Implementers Forum (USB-IF) in October 2022. It doubles the performance capabilities of USB® wired connections to external drives, 4K, and 6K displays. It’s PHY architecture based on PAM-3 signal encoding over existing 40Gbps Type-C passive cables and newly defined 80Gbps Type-C active cables allows USB4® v2 to deliver up to 120Gbps in one direction and 40Gbps in the other direction when configured asymmetrically.

Where Can USB4® v2 Be Used?

USB4® v2 allows HD videos to be stored and easily accessed on fast external drives, with minimal latency for data-heavy tasks such as video editing. This iteration also supports mobile and network storage applications, allowing laptops to combine video, audio, data, and power onto a single cable to facilitate mobile work. This also makes moving between the office, meeting rooms, and home office more seamless.

USB4® v2 Overview

The USB® Gen 4 mode of operation is supported by Electrical Layer specifications for Router Assembly. Electrical Layer specifications detail the requirements and testing methodologies for achieving reliable communication and interoperability over USB4® interconnects that employ passive or active cables.

For example, using 3-level Pulse Amplitude Modulation (PAM3) at a Baud rate of 25.6GB per Lane conveys data over the physical media. Each PAM3 symbol encodes 1.57 bits obtained through 11-bits to 7-trits mapping. Furthermore, Gen 4 Links operate with Trit Error Ratios of 1E-8 or lower without Forward Error Correction (FEC). Finally, Spread-Spectrum-Clocking (SSC) can be applied on high-speed transmission signals, with a single clock source used for all the transmitters within a USB4® Port.

USB4® v2 80 Gbps transmitter test

The following tables list out the test items for the USB4® v2 Gen4 Electrical CTS, Revision 0.9

Test ID				Test Items
3.3.1				Transmitter Equalization, Preset 0 ~ Preset 41
3.3.2				Timing Parameters subset
				UI
				SSC
				UJ / UDJ / UDJ_LF / EVEN_ODD
3.3.2				Voltage Parameters subset
				V_SWING
				TX_LEVELS_MISMATCH
				TX_SNDR
				TX_ISI_MARGIN
3.3.3				TX Frequency Variation Training
3.3.4				Electrical Idle
3.3.5				AC_CM
3.3.6				Return Loss [RL] (Informative)
3.3.7				Integrated Return Loss [IRL]
3.3.8				LFPS

Gen4 Return Loss

It’s important to note that USB® Gen4 requires a lower return loss during component selection of ESD for USB4® v2 Gen4. Additionally, the IRL test will be normative, considering the IL of the shorter trace. Results from the previous RL will be used as reference only. During the test itself, it’s important to consider impedance discontinuities, reflection, as well as component size.

Gen3

Gen4

Tx Test with SigTest

Transmitter test with sigtest must be conducted to capture presets from 0 to 41. The number of test lanes is determined by symmetry support capability.

Symmetry only: Total of 2 lanes or ports.
Asymmetry: Total of 4 lanes or ports, taking up double the test time.

USB4® v2 80Gbps Receiver test

Test ID	Test Items
4.2 Gen4 Rx TER Test
4.2.1	Gen4 Rx Equalization Training for TER Test
4.2.2	Gen4 TER test case 1
4.2.3	Gen4 TER test case 2
4.3 Gen4 Rx Frequency Variation Training Test
4.3.4	Rx Frequency Variation test case 1
4.3.5	Rx Frequency Variation test case 2
4.4 Gen4 Rx Return Loss
4.4.1	Gen4 Rx Return Loss (Informative)
4.4.2	Gen4 Rx Integrated Return Loss
4.5 Gen4 Rx LFPS

USB4® Gen4 Rx Calibration

Rx Calibration first checks the USB® Type-C passive cable assembly, which Insertion Loss Fit (ILfit) needs to be targeted to -7.5 @ 10GHz and -9.5dB @ 12.8GHz. Every single physical lane pair used for receiver testing also needs to have a tolerance range of [-0 : + 1] and [-0 : + 1.5]dB respectively.

As for the test channel with receptacle fixture de-embedded, it is recommended for the insertion loss target to be (-19dB – BERT_IL) @ 12.8GHz ± 0.5dB.

Signal Integrity Consideration

The following considerations must be made when measuring signal integrity.

SNDR (Signal to Noise Distortion Ratio )
- Crosstalk
- PCB Trace Space/ Layout
DDJ, ISI
- PCB attenuation, Impedance
- SMT Component selection and size, and placement
- Via

IRL

PCB trace impedance variation
SMT Component selection and size, and placement

USB4® Certification Requirements

All hosts, hubs, docks, and peripheral devices are required to pass USB4® compliance tests regardless of whether they are silicon or end products.

**USB® PD components are required to pass USB® PD compliance regardless of whether they are part of USB4® silicon. For components that are NOT part of USB4® silicon, it is recommended for a reference platform re-run to be conducted.

USB4® Multiple Cycle Test

USB4® Multiple Cycle Testing can be set up as per the above diagram, depending on the UUT type. Tests for A.1.1 as well as A.1.3 to A.1.6 must be run for 10 cycles to verify the following information:

Host UUT: Verify that all USB4® Hubs enumerate (repeat on each DFP)
Device UUT: Verify that UUT enumerates
Hub/Dock UUT: Verify that UUT and USB4® device enumerates

USB4® Interop CTS tests

A.1.1 Inactive Detach & Reattach
A.1.3 Sleep/Wake
A.1.4 Hiberate/Resume
A.1.5 Restart
A.1.6 Shutdown/Power On

Power up with the latest compliance methods

Check out our 2024 expert webinar for insights on the latest USB4® certification methods and the v2 update. Test, design, and debug with confidence by relying on GRL's comprehensive USB® compliance testing services.

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