Signal Integrity Webinar: Understanding Equalizers (EQ) in PCI Express®

April 29th, 2020 by Brissa Ortega

Granite River Labs (GRL) and Keysight invite you to join us for a free 1-hour live webinar to gain a greater understanding of equalizers (EQ) and their application in PCI Express for channel loss compensation.

Click here for presentation and recorded webinar

Date:   Tuesday, May 12, 2020
Time:   10:00 AM – 11:00 AM Pacific Time

Webinar Overview:
Complex systems require increasingly sophisticated means of channel loss compensation to support data link stability.  The PCI Express® (PCIe®) standard defines several equalizers for this purpose.  With the upcoming PCIe 6.0 specification supporting 64 GT/s (up to 256 GB/s via x16 configuration), effective use of equalizers becomes even more critical to successful system design.  This session will help engineers understand the fundamentals of how equalizers (EQ) work, different types of EQ including continuous time linear equalizers (CTLE) and decision feedback equalizers (DFE), how EQ are defined in the PCIe specification, and how PCIe link training works to optimize EQ settings.  We will also look at how EDA tools like Keysight’s Physical Layer Test System (PLTS) support equalizer optimization and eye simulation.


About the Presenters

Mike RessoSignal Integrity Applications Scientist, Keysight Technologies     

Mike Resso is the Signal Integrity Application Scientist in the Internet Infrastructure Solution Group of Keysight  Technologies and has over thirty years of experience in the test and measurement industry. His background includes the design and development of electro-optic test instrumentation for aerospace and commercial applications.  His most recent activity has focused on the complete multiport characterization of high speed digital interconnects using Time Domain Reflectometry and Vector Network Analysis.  He has authored over 30 professional publications including two books on signal integrity. Mike has been awarded one US patent and has twice received the Agilent “Spark of Insight” Award for his contribution to the company. He received a Bachelor of Science degree in Electrical and Computer Engineering from University of California.

Miki TakahashiExecutive Vice President of Engineering, GRL

Miki Takahashi is Executive Vice President of Engineering at Granite River Labs and has over 20 years of experience in high speed SerDes design, signal integrity design and measurement, as well as interface modeling and simulation. Miki has been working on and contributing to the PCI Express standard since v1.0.  An expert in memory bus technologies, Miki chairs the SD Association UHS Task Group driving next-generation high speed memory card PHY standards, received the SD Association Innovation and Technology Award in 2014, and has authored numerous technical whitepapers and seminars.  He received a M.S. in Material Physics from Nagoya University.

Questions?  Contact Quintin Anderson, GRL co-Founder & COO.

About Granite River Labs |
The world’s leading Engineering Services and Test Automation Solutions firm for connectivity and charging, GRL helps engineers solve tough design and validation challenges.  GRL began in 2010 with a vision to provide affordable test services to help hardware developers implement digital interface technologies as they become faster, more complex, and more challenging to test. Today, GRL has worked with hundreds of companies supporting the adoption of new and emerging technologies from our worldwide test facilities and R&D centers.